Tutorial I
June 13, 2021 (Sunday) 13:00 – 16:00 (GMT+2) (Virtual Room 1)
Neuromorphic circuits and systems
Annealing Processing AI chip and Emerging Non Volatile Memory for Next IoT era
Prof. Takayuki Kawahara Tokyo University of Science, Japan
Abstract
In this lecture, I will first outline the edge computing trend. Next, as part of the development trend of AI chips, I will explain neural networks and deep learning, and then I will explain the incorporation of learning functions, sparseness, calculation accuracy, and recognition rate. Brain type neuromorphic computing chip technology will also be reviewed. Next, I will explain the development trends of new non-volatile memory that is indispensable for low power consumption AI chips. It outlines phase change memory, ferroelectric memory, resistive memory, etc., and details STT RAM, and SOT RAM technologies in particular. For SOT RAM technology, a new bidirectional read method is described that takes advantage of the properties of spin orbit interaction to improve the stability. Then, the development of the world’s first fully coupled spin annealing AI chip to help solve combinatorial optimization problems is disclosed. It is based on a calculation method that applies a model of ferromagnets in statistical mechanics, and by converting and implementing the mechanism to LSI, it is possible to solve combinatorial optimization problems required for advanced AI processing with small area, high speed, and ultra-low power consumption. Furthermore, if we use the fully coupled type that couples all spins instead of the adjacent coupling type of the ferromagnetic model as it is, it is versatile while having a smaller area (adjacent coupling requires the square of the number of spins in fully coupled). It can solve a wide range of problems. This represents a new paradigm for edge computing. It also discusses development trends in related quantum computing initiatives.
Biography
Prof. Takayuki Kawahara, Fellow IEEE, obtained his BS, MS, and Ph.D. degrees from Kyushu University, Japan. With his MS degree, he joined Hitachi Central Research Laboratory and designed the most advanced memory chips in his 29 years career, and also one year stayed in École Polytechnique Fédérale de Lausanne. After leaving the laboratory as a Chief Researcher, he joined Tokyo University of Science in 2014 to work on developing sustainable electronics. His research group carries out cutting-edge research in the field of low-power AI circuits and systems. With more than 120 publications to his credit, he has won numerous awards, including the prizes for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology, Japan.
Tutorial II
June 13, 2021 (Sunday) 13:00 – 16:00 (GMT+2) (Virtual Room 2)
RF & microwave circuits
Negative group delay circuit and function
Prof. B. Ravelo Nanjing University of Information Science & Technology, School of Electronic & Information Engineering Nanjing, Chin
Dr. S. Lalléchère Université Clermont Auvergne, Institut Pascal, SIGMA Clermont, FranceF
Dr. G. Fontgallant Federal University of Campina Grande, Applied Electromagnetic and Microwave Lab., Campina Grande/PB, Brazil
Abstract
This tutorial is divided in three main parts. In the 1st part, the basic and fundamental theory on the NGD functions will be introduced. One of the most basic and simpler way to exercise the NGD design engineering is by considering the analogy between linear filter and NGD theory. Unfamiliar concepts of low-pass (LP), high-pass (HP), and bandpass (BP) NGD functions will be initiated during the course and canonical forms of LP and HP transfer function from first order circuits will be introduced. Then, based on the LP to BP transform, the BP canonical transfer function will be presented. In the 2nd part, illustrative examples of R, L, and C lumped components-based circuit will be given for pedagogical practice of the introduced NGD function theory. More practical microwave engineering on the design of diverse distributed topologies of NGD circuits will be discussed. The design method of microstrip NGD circuits will be revealed. The different steps from the S-matrix modelling to NGD analysis and examination of NGD calculated, simulated, and measured results will be addressed. In the last part, two different applications will be explored. The first application is based on LP NGD function. This application aims to equalize the RC- and RLC-distortion with LP NGD active circuits. The second application is focused on the design of frequency independent phase shifter with BP NGD active circuit.
Biography
Prof. Blaise Ravelo is currently Professor at Nanjing University of Information Science & Technology, China. He is a pioneer of the NGD concept (t<0) and its applications. He was research director of 10 PhD students (9 defended), postdocs, research engineers and Master internships. With USA, Chinese, Indian, European, and African partners, he is actively involved and contributes on several international research projects. His Google scholar h-index in 2020 is 21. He is (co-)authors of more than 310 scientific research papers published in international conference, journals and books.
Tutorial III
June 13, 2021 (Sunday) 16:15 – 19:15 (GMT+2) (Virtual Room 1)
CAD and design tools
System-Level considerations for the modelling, the design and the characterization of PLL-Devices
Dr. Christian Hedayat Fraunhofer Institute for Electronic Nano Systems – Dpt. Advanced System Engineering, University of Paderborn, Paderborn, Germany
Dr. Ivan Rodrigo Kaufmann Fraunhofer Institute for Electronic Nano Systems – Dpt. Advanced System Engineering, University of Paderborn, Paderborn, Germany
Dr. Christian Hangmann Fraunhofer Institute for Electronic Nano Systems – Dpt. Advanced System Engineering, University of Paderborn, Paderborn, Germany
Prof. Ulrich Hilleringmann Fraunhofer Institute for Electronic Nano Systems – Dpt. Advanced System Engineering, University of Paderborn, Paderborn, Germany
Patrick Deutschmann Fraunhofer Institute for Electronic Nano Systems – Dpt. Advanced System Engineering, University of Paderborn, Paderborn, Germany
Abstract
Phase Locked Loops (PLL) are essential components of electronic devices used primarily in communication and synchronisation applications. Their applicability ranges from frequency synthesis toward phase and frequency modulation and demodulation, jitter filtering, clock and data recovering, Doppler radar… A PLL is basically a feedback control system comprising mainly a voltage-controlled oscillator which frequency is tuned by a voltage until reaching a desired value related to the reference one. Historically its invention goes back to Henri de Bellescize in the early 1930’s as a full analogue system. But its importance raised dramatically when being used for the synchronization of the tube horizontal and vertical scans in TV applications. With the introduction of integrated circuits mid 1960’s, mixed signal PLLs (MS-PLL) combining analogue and digital parts became increasingly unavoidable in all areas mentioned above and nowadays they are implemented in complex systems like processors, where clock generation is embedded. The modelling of such systems is challenging due to the mixture of analogue and digital domains. Analytical descriptions are therefore mostly based on simplifying assumptions and a priori linearization whereby the characterization of the strongly non-linear behaviour due to the switching nature of the digital parts becomes challenging. On one hand quasi-continuous-time modelling is a good choice for the average description of the in-lock behaviour while quasi-discrete-time modelling is suitable for stability assessment close to the settled state. On the other hand, transistor level simulations perform a very accurate prediction of the circuit electrical behaviour, but they require huge computational efforts. In this way, transistor level simulations give only few possibilities of analysing and debugging the design in the case of unexpected results. Thus, the simultaneously fast and accurate modelling, simulation and analysis of the MS-PLL behaviour may be one of the biggest challenges for the design of them. In this tutorial, we will present the basic concepts of the PLL architectures by analysing the different types (linear, digital…) considering first the systems as being ideal. Different modelling and simulation approaches will be presented on the system-level. A special focus will lay on the non-linear locking behaviour that any careful design should consider. In a further step, the effect of the typical loop non-idealities and noise will be explored. All along this tutorial, a design guideline with a step-by-step methodology is aimed, giving some guidance for the student or the beginning designer to understand the most important system-level aspects when designing a PLL.
Biography
Christian Hedayat studied Physics at the University of Nice Sophia‐Antipolis, France. In 1993, he obtained his Masters of Electrical Engineering, with focus on Telecommunication and Antenna Design. In 1998 he obtained his Ph.D. degree in the area of modelling of mixed‐signal PLL systems in collaboration with Texas Instruments France. He worked then with Atmel France as an analogue IC designer before joining in 2004 the University of Paderborn and the Fraunhofer Institute for Reliability and Micro Integration in order to work on fast simulation models of mixed-signal devices for EMR purposes. Since July 2008, Dr. Hedayat is leading the department of Advanced System Engineering (ASE) within the Fraunhofer ENAS, managing several European industrial projects related to automotive and communication applications. His research team interests focus on RF /RFID systems, modelling of mixed signal systems for EMC, EMR and RF purposes and the design of wireless energy transfer systems. He has published more than 50 technical papers on the subjects of his work and is teaching at the University of Paderborn.
Tutorial IV
June 13, 2021 (Sunday) 16:15 – 19:15 (GMT+2) (Virtual Room 2)
RF & microwave circuits
More-than-Moore Modules and Heterogeneous Integration Technologies for mm-wave and THz Applications
Dr. –Ing. Mehmet Kaynak IHP Leibniz-Institut für innovative Mikroelektronik, Frankfurt Oder, Germany
Abstract
The fast and strong development on heterogeneous integration technologies, on one side has solved many issues such as miniaturization and integration; but creates new challenges such as electromagnetic, thermal and mechanical reliability and robustness of these highly dense systems. The GaAs or GaN integrated systems have always the challenge of thermal and mechanical stability. Such challenge is significantly increases with a potential hetero integration of it with any other silicon based die. On the other side, the array type systems have significant amount of power in a very small area. Both issues get worse with the increased frequency (i.e. at mm-wave and THz) due to the lower efficiency of the active devices (i.e. transistors) and also need of a very dense integration because of the lower wave-length. All these aforementioned challenges have initiated a very hot research area of circuit-package interaction where the chip and package has to be considered together from electromagnetic, thermal and mechanical aspects. Such challenge is a complex multi-disciplinary problem and needs of understanding all the corresponding disciplines. In addition, a strong multi-discipline finite-element-solutions are necessary for the modeling and simulation of such complex systems. In this talk, the latest developments regarding the high-speed devices and circuits based on SiGe HBTs at IHP will be discussed. The “More-than-Moore” modules for multi-functional device and the latest heterogeneous integration techniques for advanced packaging will be presented with some advance multi-physics simulations.
Biography
Dr. –Ing Mehmet Kaynak received his B.S degree from Electronics and Communication Engineering Department of Istanbul Technical University (ITU) in 2004, took the M.S degree from Microelectronic program of Sabanci University, Istanbul, Turkey in 2006 and received the PhD degree from Technical University of Berlin, Berlin Germany in 2014. He joined the technology group of IHP Microelectronics, Frankfurt (Oder), Germany in 2008. From 2008 to 2015, he has led the MEMS development at IHP and from 2015-2020, he has led the department head of Technology at IHP. Dr. Kaynak is being affiliated as Adjunct Professor at Sabanci University, Turkey.